The present invention generally relates to a signal processing apparatus for video cassette recorders (VCR), and more particularly to a pilot burst gate pulse generating system suitable for extracting a pilot burst signal from a composite video signal based upon the S-VHS standard of the PAL system.
In a composite video signal based upon the VHS standard of the PAL system, there are included a burst signal having a duration (width) of 4 .mu.sec which is introduced thereinto at a timing elapsed by 4 .mu.sec from the active edge of a horizontal synchronizing signal and further included a video signal which is introduced thereinto at a timing delayed by a predetermined time period from the burst signal. On the other hand, in a composite video signal based upon the S-VHS standard of the PAL system, there are included a pilot burst signal having a duration of 2.4 .mu.sec which is introduced thereinto at a timing elapsed by 0.8 .mu.sec from the active edge of a horizontal synchronizing signal and further included the same burst signal and video signal as in the aforementioned VHS standard which are introduced thereinto at a timing after the introduction of the pilot burst signal. In reproducing the video signal from the composite video signal satisfying the S-VHS standard, it is required to produce a pilot burst gate pulse signal on the basis of the horizontal synchronizing signal so as to extract the pilot burst signal by the produced pilot burst gate pulse signal.
FIG. 1 is a block diagram showing a prior art pilot burst gate pulse generating system and FIG. 2 is a timing chart showing voltage waveforms at portions of the pilot burst gate pulse generating system as shown in FIG. 1. In FIGS. 1 and 2, the generating system is provided with a first input terminal 1 responsive to a clock signal and further equipped with a second input terminal 2 responsive to a horizontal synchronizing signal (HSS) of a television signal. The second input terminal 2 is coupled to a reset pulse generating circuit 3 which is triggered in response to the active edge of the inputted horizontal synchronizing signal so as to generate reset pulses 3a having a duration corresponding to one or two clock pulse repetition periods. The reset pulse 3a is supplied to the reset terminal of a counter 4 which in turn enters into a reset condition. The counter 4 is also coupled to the first input terminal 1 to start the counting operation in response to the clock signal after being reset by the resent pulse 3a. The repetitive counting operation of the counter 4 is illustrated in analog form at 4a in FIG. 2. When the count value reaches a first value A, the counter 4 generates a first pulse through an output terminal A, and when reaching a second value B, it generates a second pulse through an output terminal B. These first and second pulses are supplied through inverters 5 and 6 to first and second latch circuits 7 and 8, respectively. The first latch circuit 7 is composed of NAND gates 9 and 10 which are cross-coupled to each other and the second latch circuit 8 is similarly composed of NAND gates 11 and 12 which are cross-coupled to each other. One input terminals of the first and second latch circuits 7 and 8 are responsive to the output pulses of the inverters 5 and 6, respectively, and the other terminals thereof are responsive to the reset pulse 3a from the reset pulse generating circuit 3. The output pulse of the second latch circuit 8 is supplied to an inverter 13 so as to be inverted to a pulse as illustrated at 13a in FIG. 2 and then supplied to one input terminal of an AND gate 14. The output pulse of the first latch circuit 7, as illustrated at 7a in FIG. 2, is led to the other input terminal of the AND gate 14, thereby obtaining a pilot burst gate pulse 15a as illustrated at 15a in FIG. 2.
There is a problem with arises with such a conventional pilot burst gate pulse generating system, however, in that extreme difficulty is encountered to generate a pilot burst gate pulse slightly delayed from the leading (rising) edge of the horizontal synchronizing signal (HSS) supplied to the second input terminal 2 (in the above-mentioned S-VHS standard, 0.8 .mu.sec +0.3 .mu.sec), because of resulting in a delay of approximately 0.8 .mu.sec when separating the horizontal synchronizing signal from the composite synchronizing signal of the television signal. Thus, it is impossible to generate a pilot burst gate pulse at a timing delayed by 0.8 .mu.sec with respect to the rising edge of the horizontal synchronizing signal before the synchronous separation..